This invention relates to power supplies and more specifically to switching power supplies.
It is known in the art to provide switching power supplies such as power supply 10 of FIG. 1 which receives a first DC voltage Vin on an input terminal 12 and generates therefrom a second DC voltage Vout on an output terminal 14. Power supply 10 provides output voltage Vout across a load modeled as resistor RL.
Power supply 10 includes an inductor L1 coupled between input terminal 12 and a node N1. Coupled between node N1 and ground is an N channel MOS transistor Q1 and a resistor R1. Transistor Q1 periodically turns on and off in response to a signal from a logic circuit 16. When transistor Q1 is on, current flows through input terminal 12, inductor L1, transistor Q1, and resistor R1. Since the resistance of resistor R1 is small, most of the voltage drop Vin appears across inductor L1. As is known in the art, when a constant voltage is applied across an inductor, the current through the inductor increases linearly with time. Thus, the current through inductor L1 increases until transistor Q1 turns off. When transistor Q1 turns off, current flows through input terminal 12, through inductor L1, through a diode D1, and through parallel connected output capacitor C1 and load RL. The amount of power delivered to load RL depends upon the amount of energy stored in inductor L1 when transistor Q1 turns off, which in turn depends upon the amount of time that transistor Q1 remains on during each switching cycle of transistor Q1. Diode D1 prevents output capacitor C1 from discharging through transistor Q1 or inductor L1.
Transistor Q1 turns on and off at a constant frequency but with a duty cycle which varies in response to output voltage Vout. Specifically, transistor Q1 turns on in response to a clock signal CLK received on a clock terminal 17 and turns off in response to output voltage Vout. Thus, if output voltage Vout decreases, the on-time of transistor Q1 increases, thereby causing inductor L1 to store more energy during each cycle while transistor Q1 is on, and thus causing inductor L1 to deliver more power to load RL when transistor Q1 is off. Conversely, if output voltage Vout increases, the on-time of transistor Q1 decreases, causing inductor L1 to deliver less power to load RL.
Power supply 10 includes a voltage divider which includes resistors R2 and R3 and provides voltage V1 proportional to output voltage Vout. Voltage V1 is compared to a reference voltage Vref by an amplifier 18 which generates a voltage V2 proportional to the difference between voltage V1 and reference voltage Vref. Voltage V2 is presented to an inverting input lead of a comparator 20. The noninverting input lead of comparator 20 receives a voltage V3 present at the node between transistor Q1 and resistor R1. The relationship between voltage V2, voltage V3, clock signal CLK and the on-time of transistor Q1 is illustrated in the timing diagram of FIG. 2.
Referring to FIG. 2, it is seen that when transistor Q1 turns on in response to the rising clock signal CLK, a short voltage spike S1 appears across resistor R1 for two reasons First, because of the gate-source capacitance of transistor Q1, when a high voltage is first applied to the gate of transistor Q1 causing transistor Q1 to turn on, a pulse appears at the source of transistor Q1 and therefore across resistor R1. Second, because of the capacitance of the various elements coupled to node N1, when transistor Q1 first turns on, the change in voltage on this capacitance at node N1 causes current to flow through transistor Q1 and resistor R1, adding to the voltage spike across resistor R1.
Following the settling of voltage spike S1, voltage V3 across resistor R1 steadily increases because when transistor Q1 is on, the current through inductor L1 increases linearly with time and therefore, the current through resistor R1, and thus voltage V3 across resistor R1, increases linearly with time. When voltage V3 increases past voltage V2 (as described above, voltage V2 is proportional to the difference between voltage V1 and reference voltage Vref), the output signal from comparator 20 provides a pulse to logic circuit 16 causing logic circuit 16 to turn off transistor Q1. Transistor Q1 remains off until the next rising edge of clock signal CLK, at which time transistor Q1 turns on again and remains on until comparator 20 provides another pulse to logic circuit 16.
If output voltage Vout decreases, the difference between voltage Vref and voltage V1 increases, voltage V2 increases (e.g. to a value V2' illustrated in FIG. 2), and therefore, transistor Q1 remains on for a longer period of time. Because of this, during the on-time of transistor Q1, more energy is stored in inductor L1, which means that more energy is provided to output load RL each cycle when transistor Q1 is turned off. In this way, power supply 10 counteracts a decrease in output.voltage Vout by providing more power to load RL, and vice versa. Of importance, switching transistor Q1 is always off when clock signal CLK is low, preventing switching transistor Q1 from having a duty cycle greater than the duty cycle of clock signal CLK, thereby allowing time for energy stored in inductor L1 to be transferred to load RL and preventing excessive current through and destruction of transistor Q1.
As can be seen in FIG. 2, if voltage spike S1 is greater than voltage V2, comparator 20 cannot distinguish between spike S1 and the normal voltage ramp associated with the waveform of voltage V3. Accordingly, if voltage spike S1 becomes greater than voltage V2, comparator 20 will provide a pulse to logic circuit 16 almost immediately after transistor Q1 turns on, thereby causing comparator 20 to fail to regulate output voltage Vout properly.